1. Field of the Invention
The invention relates to a system LSI (Large Scale Integration) having a plurality of circuit blocks integrated therein and more particularly to a clock delay compensation circuit for preventing production of off-specification products due to production tolerance on a manufacturing process for the system LSI.
2. Description of the Related Art
FIG. 2 of the accompanying drawings is a schematic block diagram illustrating a conventional system LSI which is formed by a logic circuit 10 and a ROM (Read Only Memory) 20. Such system LSI is disclosed, for example, in Japanese Patent Kokai No. 11-88142.
The logic circuit 10 includes a plurality of circuit blocks such as a RAM (Random Access Memory) (not shown) and an input/output circuit (not shown) in addition to a CPU (Central Processing Unit) 11. These circuit blocks including the CPU 11 receive a clock signal CK0 via a clock tree buffer 12 where a phase of the clock signal CK0 is adjusted.
A memory content stored in the ROM 20, such as a program and fixed data to be processed in the CPU 11, is output as read data RD when a region having the memory content is specified by an address signal ADR supplied from the CPU 11. To a clock terminal C of the ROM 20, a clock signal CK1 used for read-timing is supplied from the clock tree buffer 12 of the logic circuit 10.
When the system LSI receives the clock signal CK0 representing the reference of the operation timing, the phases of the clock signals to be supplied to the circuit blocks including the ROM 20 are adjusted by the clock tree buffer 12, and then the adjusted clock signals are respectively supplied to the circuit blocks. Accordingly, each circuit block receives the clock signal in accordance with the timing that has been given due consideration to a delay caused by a difference of the signal route concerned, thereby making it possible for the circuit block to timely read the data supplied from a preceding circuit block.
Miniaturization of the system LSI and lowering of voltage in the LSI may increase malfunction due to an operation noise within the LSI, i.e., a noise caused by a switching operation of a transistor included in the LSI, and furthermore they may impact on a product yield due to production tolerance on a wafer process.
Scaling up of the system LSI increases the number of logic circuits that operate simultaneously, which leads to concern about off-specification products caused by the operation noise. As a countermeasure, such design approach is sometimes employed that shifts the timing of the clock signal of the logic circuit 10 from that of the ROM 20 within an extent that ensures a regular operation over the system LSI, so that the number of the circuit blocks operating simultaneously is reduced and thus the operation noise is reduced.
Even though the circuit blocks are appropriately arranged and the delay buffer for the clock signal is appropriately designed in a design phase in order not to synchronize the operations among the circuit blocks, the system LSI may not function in an expected manner due to production tolerance employed on a wafer process. Consequently, the timings of the clock signals may unexpectedly synchronize with each other, and thus the system LSI including the above circuit block may become an off-specification product.